基于软件无线电架构的多模导航SoC芯片设计

Design of multimode navigation SoC chip based on software radio architecture

当前多个全球卫星导航系统(GNSS)信号的频率及体制不同,传统的基于超外差或低中频架构的无线接收机需要在模拟域通过复杂的模拟电路进行下变频、滤波、放大、模数转换等信号处理,且需要多个模拟通道来处理多模信号,这给多模导航一体化SoC芯片的设计带来了极大的挑战。针对上述情况,文中基于模拟最小化、数字最大化的思想,通过芯片内部集成高增益射频放大器、低功耗的高速模数转换器、低抖动的时钟锁相环以及数字信号处理的基带处理及CPU电路,创新性地提出一种基于软件无线电架构的多模导航SoC芯片。然后,进行55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证。测试结果表明,文中的SoC芯片具备多模导航功能,定位精度可达到2.5 m,授时精度为55.9 ns,测速精度为0.06 m/s,功耗为81 mW,芯片面积大小为6 230μm×4 480μm。所提出的多模导航SoC芯片与市场主流产品性能相当,可满足导航系统需求。

At present,the frequencies and structures of signals of multiple global navigation satellite systems(GNSSs)are different. The traditional wireless receiver based on superheterodyne or low/intermediate frequency architecture needs to execute signal processing(down conversion,filtering,amplification and analog-to-digital conversion)in the analog domain by means of complex analog circuits,and multiple analog channels are required to process multimode signals,which brings great challenges to the design of multimode navigation integrated SoC chip. On the basis of the idea of analog minimization and digital maximization,a multimode navigation SoC chip based on software radio architecture is proposed innovatively by integrating the high gain radio frequency amplifier,the low-power high-speed ADC(analog to digital converter),the low-jitter clock phase-lock loop,and the baseband processing and CPU circuit for digital signal processing. The 55 nm CMOS process circuit design,layout design,simulation and silicon wafer verification are conducted. The testing results show that the SoC chip has multimode navigation function,its positioning accuracy is 2.5 m,its timing accuracy is 55.9 ns,its velocity measurement accuracy is 0.06m/s,its power consumption is 81 mW,and its area is 6230 μm × 4480 μm. The performance of the proposed multimode navigation SoC chip is equivalent to that of the mainstream products in the market,which can meet the requirements of the navigation system.