一种用于高速高精度锁相环的Sigma-Delta调制器设计

A Sigma-Delta Modulator Design for High-Speed and High-Precision PLL

针对MASH结构Sigma-Delta调制器输入位宽过高时速度受限的问题,结合Sigma-Delta结构特点,在不改变算法功能的前提下,设计一种并行MASH累加器结构的Sigma-Delta调制器,速度得到了大幅提升,可以用于高速高精度锁相环(Phase Locked Loop,PLL)。首先使用Verilog HDL硬件语言实现了RTL级描述,并且基于0.11μm CMOS工艺使用DC工具进行了综合,并对功能进行了仿真。仿真结果表明,改进后的结构能够与传统结构进行同位替换。综合结果表明,改进后的分数调制器输入位宽为32位时,与传统的分数型调制器相比,速度提升了23.77%,面积仅增加2.99%,能够有效改善Sigma-Delta调制器速度受限的问题。

Aiming at the problem that the speed is limited when the input bit width of the MASH structure Sigma-Delta modulator is too high, according to the characteristics of the Sigma-Delta structure, without changing the function of the algorithm, a sigma-delta modulation with a parallel MASH accumulator structure is designed. The speed has been greatly improved, and can be used for highspeed and high-precision Phase Locked Loop(PLL). First, the RTL-level description is implemented using Verilog HDL hardware language, and the DC tool is used for synthesis based on the 0.11μm CMOS process, and the function is post-simulated. The simulation results show that the improved structure can be replaced with the traditional structure. The synthesis results show that, when the input bit width of the improved fractional modulator is 32 bits, compared with the traditional fractional modulator, the speed is increased by 23.77%, and the area is only increased by 2.99%, which can effectively improve the speed limitation of the Sigma-Delta modulator.