一种改进的Turbo码结构设计及DSP实现

An Improved Architecture Design and DSP Implementation of Turbo Code

针对传统Turbo码在高码率场景下的错误平层问题,以及通信数据链项目中更大的码率范围需求,研究了增强型Turbo码方案和并行译码算法。采用咬尾码结构解决了译码错误平层问题,设计了更低码率的编译码器结构,以满足更低的码率范围,并取得了0.4~0.6 dB的误码率(Bit Error Ratio,BER)性能提升。最后结合并行译码算法和数字信号处理器(Digital Signal Processor,DSP)(TMS320C668)优化技术,对译码器的定点实现进行了优化,使译码计算取得了2.6~3.7的加速比。仿真和项目验证表明该设计具有良好的性能和较高的工程实践价值。

Aiming at the error floor problem of traditional Turbo code in high bit rate scenarios, and the larger bit rate range requirement in data link projects of communication, the scheme of enhanced Turbo code and parallel decoding algorithm are explored. The tail-biting code structure is used to solve the decoding error floor problem. A lower bit rate code structure is designed to meet the lower bit rate range, and the BER(Bit Error Ratio) performance is improved by 0.4~0.6 dB. Finally, combined with the parallel decoding algorithm and the optimizing technology of Digital Signal Processor(TMS320C6678), the fixed-point implementation of the decoder is optimized, so that the decoding calculation obtains a speedup of 2.6~3.7. Simulation and project verification indicate that the design has good performance and high engineering practice value.