一种基于SRAM密钥存储方案的低功耗AES加密解密器

A low power AES encryption and decryption device based on SRAM key storage scheme

本文设计了一款低功耗小面积的AES加密解密器。在使用ECB/CBC/CTR链接算法的条件下,采用了40x32 SRAM方案的密钥存储实现的密钥扩展模块、32bit数据路径实现的改进的AES轮变换结构,有效降低了AES加密解密器的整体面积和加密或解密过程中的动态功耗。在Synopsys平台的设计流程中,采用SMIC 55nm工艺库,50MHz的频率下,优化后的AES加密解密器的面积比未优化的AES降低了46.4%,加密运算时的功耗降低了42.4%,解密运算时的功耗降低了37.8%。

This paper designs an AES encryption and decryption device with low power consumption and small area.Under the condition of using ECB/CBC/CTR link algorithm,the key expansion module realized by key storage of 40x32 SRAM scheme and the improved AES round conversion structure realized by 32bit data path are adopted,which effectively reduces the overall area of AES encryption and decryptor and the dynamic power consumption in the process of encryption or decryption.In the design process of Synopsys platform,SMIC 55nm process library is adopted.Under the frequency of 50MHz,the area of optimized AES encryption and decryption device is 46.4% lower than that of non optimized AES,the power consumption during encryption operation is 42.4% lower,and the power consumption during decryption operation is 37.8%.