RISC V标准指令集的六级流水线设计

Six-stage Pipeline Design for RISC-V Standard Instruction Set

基于RISC V标准指令集,提出一种六级流水线设计方法。首先,分析了流水线级数对处理器性能的影响,在经典五级流水线的基础上将流水线划分为6个阶段,缩短时延,提高主频。其次,为解决流水线中的冒险问题,采用定向前推和插入纵向气泡的方式处理数据冒险问题,使用流水线冲刷解决流水线中控制冒险问题。最后,在EDA工具中,采用RISC V标准指令集对本设计进行仿真测试,并在FPGA上实现,运行时钟频率可达78.2 MHz。

Based on the RISC V standard instruction set,a six-stage pipeline design is designed in the paper.First of all,this article analyzes the impact of pipeline stages on processor performance,and divides the pipeline into six-stage on the basis of the classic five-stage pipeline,reducing the delay to improve the main frequency.Secondly,in order to solve the risk problem in the pipeline,this design adopts the method of pushing forward and inserting longitudinal bubbles to deal with the data adventure problem,and uses the pipeline flushing to solve the control risk problem in the pipeline.Finally,in the EDA tool,the design is simulated using the RISC V standard instruction set and implemented on the FPGA,running at clock frequencies up to 78.2 MHz.