一种低延迟折叠插值12位1.5 GS/s ADC

A Low Latency Folding and Interpolation 12 bit 1.5 GS/s ADC

基于4级级联折叠插值架构,提出了一种12位ADC。电路采用0.18μm SiGe BiCMOS工艺设计。单核达到1.5 GS/s的转换速度,接口输出为2-lane LVDS,延迟时间小于7 ns。前端采样保持电路和折叠插值量化器采用纯双极设计,在不修调的情况下可达到12位量化精度。最后,给出版图设计要点和测试结果。

Based on a 4-stage cascade folding interpolation architecture,a 12-bit ADC was presented.The circuit was designed in a 0.18μm SiGe BiCMOS process.The single core achieved a conversion speed of 1.5 GS/s,the output interface was 2-lane LVDS,and the latency was less than 7 ns.The front-end sample/hold circuit and folding interpolation quantizer adopted pure bipolar design,which could achieve 12 bit quantization accuracy without trimming.Finally,the design points and test results of the published layout were given.