摘要
为了解决多路视频并行输入缓冲处理问题,提出了一种以FPGA为核心的通用多路视频输入处理系统。通过规划对应的多时钟域处理方案,建立适用的视频缓冲控制模式,为后续实现视频缩放拼接、画中画显示等功能提供解决方案。借助该视频缓冲控制模式,本系统实现四进一出视频拼接、画中画叠加等显示功能,在12.5 GB/s存储带宽条件下支持1080P 60帧视频格式下的4路视频输入和1路输出处理。
In order to solve the problem of buffer processing of multi-channel HD video parallel input,a multi video input processing system based on FPGA hardware platform is designed.An adaptable video buffer control mode is established by planning the corresponding multi-clock domain processing scheme,which provides solutions for the subsequent realization of video splicing,picture-in-picture display and other functions.The proposed system can support 4 input and 1 output of 1080 P@60 fps video channels based on 12.5 GB/s memory bandwidth.
作者
宋长骏
汤勇明
SONG Changjun;TANG Yongming(Display R&D Center,Southeast University,Nanjing Jiangsu 210096,China)
出处
《电子器件》
CAS
北大核心
2022年第4期805-809,共5页
Chinese Journal of Electron Devices
关键词
多视频输入处理
跨时钟设计
FPGA
multi video input processing
clock domain crossing design
FPGA
