基于FPGA的高性能ADC的设计与实现

Design and Implementation of High Performance ADC Based on FPGA

模数转换器(ADC)作为连接模拟世界和数字世界的桥梁,在工业界和学术界一直发挥着重要的作用,然而实现高性能、低成本的ADC一直以来都是业界的一个难点。提出一种基于现场可编程门阵列(FPGA)实现高性能ADC的方法,主要方法是利用FPGA的差分输入作为比较器,一端外接电阻和比较器的寄生电容构成RC电路,通过充放电产生参考电压,另一端作为模拟信号的输入与参考电压进行比较,最后通过构建时间数字转换器(TDC)测量输入信号和参考电压相等的时刻再根据参考电压与充放电时间的关系从而实现模拟信号到数字信号的转换。实验结果表明该ADC采样率可达800 MSa/s,量程为0.45~1.35 V,有效位为6.1位,积分线性度(DNL)为-0.93~0.94 LSB,微分线性度(INL)为-0.78~0.83 LSB,能够满足大部分应用需求并且展示出良好的可扩展性。

Analog-to-digital converter( ADC),as a bridge between the analog and digital world,has been playing an important role in industry and academia.However,it has always been a challenge to design a high performance and low cost ADC.A high performance ADC based on field programmable gate array( FPGA) is proposed in this paper.The main method is to use the differential input of FPGA as the comparator.One end is connected with the external resistor to form the RC circuit with the parasitic capacitor of the comparator,which generates the reference voltage through charge and discharge,and the other end is used as the analog signal input to compare with the reference voltage.Finally,time-digital converter( TDC) is constructed to measure the moment when the voltage of the input signal equals the reference voltage to realize the conversion of analog signal to digital signal.The experimental results show that the ADC can achieve a sampling rate of 800 MSa/s with a 6.1-bit resolution for signals ranging from 0.45 to 1.35 V.The differential nonlinearity( DNL) ranges from-0.93 to 0.94 LSB,and the integral nonlinearity( INL) is in the range between-0.78 to 0.83 LSB,showing that the ADC can meet most application requirements and demonstrate good scalability.