基于FPGA的改进的排序QR分解实现

Implementation of Improved Sorted QR Decomposition on FPGA

MIMO技术虽然可以提高频谱的利用率,但是多维度的信号处理为MIMO信号的检测带来了极大的挑战.在对各类MIMO检测算法分析的基础上,选择非线性QR分解算法作为研究对象.为了获取更高的检测性能,进一步研究了排序的QR分解并提出了基于L1范数的排序方案.Matlab性能仿真显示,基于L1范数的排序策略和基于L2范数的排序策略对MIMO系统检测性能的影响基本一致,但采用L1范数降低了计算复杂度.在此基础上,设计了基于FPGA的利用Givens旋转改进的排序QR分解的硬件电路结构.在4×4信道矩阵的分解实现中,相较于L2范数求解,L1范数在单个列范数计算中组合逻辑资源至少节省了29.2%,触发器资源至少节省了32.4%.整体结构设计与同等规模的类似结构相比,主频时钟得到明显改善.

Although Multiple-Input Multiple-Output(MIMO)technology can improve the utilization rate of the spectrum,multi-dimensional signal processing brings great challenges to the detection of MIMO signals.Based on the analysis of various MIMO detection algorithms,the nonlinear QR decomposition algorithm is selected as the research object.In order to obtain a higher performance of detection,the sorted QR decomposition is further studied and the sorting scheme based on the L1-norm is proposed.Using Matlab for performance simulation,the L1-norm sorting strategy and the L2-norm sorting strategy have the same impact on the MIMO system,but the L1-norm sorting strategy reduces the computational complexity.On this basis,the hardware structure of the improved sorted QR decomposition by Givens rotation on FPGA is proposed.Compared with the solution of the L2-norm,the L1-norm strategy reduces at least 29.2%combinational logic resources and 32.4%register resources when calculating a single-column norm in the realization of 4×4 channel matrix decomposition.By comparing the design of the integral structure and similar dimension one,the frequency of the operating clock is significantly improved.