应用于14bit逐次逼近型ADC的前台数字校准算法

Foreground Digital Calibration Algorithm for 14 bit Successive Approximation ADC

介绍了一种应用于14bit逐次逼近型模数转换器(SARADC)的前台数字校准算法。为了减少面积并提高匹配精度,采用了电容阵列式的数模转换器(DAC)架构;为了提高ADC的信噪比,采用了差分输入的结构;而针对电容阵列中电容失配对ADC性能的影响,提出了一种可存储、可对电容误差进行纠正的前台数字算法。使用接近理想的DAC阵列对失配较大的电容阵列进行误差纠正迭代,并通过1024次的累加迭代消除了噪声,得到了真实的电容权重。在校准之后,信噪失真比(SNDR)达到了82.4dB,无杂散动态范围(SFDR)达到了93.0dB。

A foreground digital calibration algorithm for 14 bit successive approximation analog-to-digital converter(SAR ADC)is introduced.In order to reduce the area and improve the matching accuracy,a capacitor array digital-to-analog converter(DAC)architecture is adopted.In order to improve the signal to noise ratio of the ADC,a differential input structure is used.For the influence of capaciance mismatch in capacitor array on ADC performance,a foreground digital algorithm that can be stored to correct the capacitance error is proposed.The large mismatched capacitor array is corrected by an error-correcting iteration using a near-ideal DAC array,and the true capacitance weight is obtained by eliminating noise through 1024 cumulative iterations.After calibration,the signal to noise distortion ratio(SNDR)reaches 82.4 d B,and the stray free dynamic range(SFDR)reaches 93.0 d B.