抑制CMOS输出端口反向漏电设计

Design of Suppressing Reverse Leakage of CMOS Output Port

提出了抑制CMOS输出端口反向漏电的结构,当电源端接地或者悬空,CMOS输出端口接高电平时,通过优化控制逻辑,由输出端口为电路提供电源电压,从而抑制了输出端口对电源端口的漏电。以华润微电子0.25μm 5 V工艺实现电路版图并流片,典型漏电为0.01μA。

A structure to suppress the reverse leakage of CMOS output port is proposed.When the power terminal is grounded or suspended,and the CMOS output port is connected to a high level,the output port provides the power voltage for the circuit by optimizing the control logic,so as to suppress the leakage of output port to power port.Based on China Resources Microelectronics 0.25μm 5 V process,parallel flow of circuit layout is realized,and the typical leakage is 0.01μA.