一种片上嵌入式Flash测试接口的设计

Design of an on-chip Flash memory test interface

Flash存储器具有功耗低、存储容量大、体积小等特点,被广泛应用于嵌入式系统。目前Flash存储器多数使用串行接口进行擦写测试,存在着测试效率低、测试成本高等问题。针对以上问题,设计并实现了一种片上嵌入式Flash的测试接口。结合片上嵌入式Flash的接口特点和时序要求,设计了基于多线SPI的测试接口,并在确保稳定性的情况下实现了对多块Flash存储器并行测试的设计,提高了测试速度。通过NCverilog仿真结果表明,该设计有效缩短了测试时间,达到了测试要求,并成功应用于一款32位浮点微处理器中。

Flash has the charceteristics of low power consumption,large storage capacity and small volume,is widely used in embedded systems.Flash usually uses serial interface for erasing and programing test,which has the problems of low test efficiency and high test cost.The design and implementation of a test for Flash on chip is presented in this paper.By analyzing the interface and timing requirements of Flash on chip,a test interface based on multi-line SPI is designed,and the parallel test designed of Flash memories is realized under the condition of ensuring stability,which improves the test speed.The NCverilog simulation results show that the design effectively shortens the test time,meets the test requirements,and is successfully applied to a 32-bit floating-point microprocessor.