一种指令级动态可重构浮点处理器设计

Design of an instruction-level dynamically reconfigurable floating-point processor

针对高性能计算中非规则寻址模式任务的加速需求,文章设计了一种指令级动态可重构浮点处理器(dynamically reconfigurable floating-point processor, DRFP),区别于传统的可重构处理器,引入一种基于融合指令的实现方式,使得该处理器兼具动态重构和乱序执行能力。该处理器作为主要计算核心集成于一款异构多核系统芯片,并在Xilinx Ultrascale系列xcvu440的FPGA芯片上进行了原型验证,系统可以稳定工作在120 MHz。实验结果表明,该处理器在兼顾高性能的同时相较于已有工作能更好地适应非规则运算,且性能提高近3倍。

Aiming at the acceleration requirements of tasks with irregular addressing modes in high-performance computing, this paper designs an instruction-level dynamically reconfigurable floating-point processor(DRFP). Different from traditional reconfigurable processors, this paper introduces an implementation method based on fusion instructions, which enables the processor to have the ability of dynamic reconstruction and out-of-order execution. The processor is integrated into a heterogeneous multi-core system chip as the main computing core, and prototype verification has been made on the Xilinx Ultrascale series FPGA chip named xcvu440. The system can work stably at 120 MHz. Experimental results show that the processor can better adapt to irregular operations compared with existing work while taking into account high performance, and the performance is improved nearly three times than that of existing work.