同步JK触发器门级建模仿真讨论

Discussion on Gate Level Modeling and Simulation of Synchronous JK Trigger

同步JK触发器是“数字电路与逻辑设计”课程中重要的一种触发器单元。针对教材等资料普遍采用分析结论进行行为级建模的仿真不能反映触发器真正功能这一问题,提出了改进的门级建模仿真方法,对两个与门的不同延时情况也进行了详细分析,指出了部分文献和教材中的错误。

Synchronous JK flip-flop is an important flip-flop unit in the course of Digital Circuit and Logic Design. Aiming at the problem that the simulation of behavior level modeling commonly used in teaching materials can not reflect the real function of the trigger, an improved gate level modeling and simulation method is proposed, the different delays of two and gates are also analyzed in detail, and the errors in some papers and teaching materials are pointed out.