基于递归学习的静态逻辑电路功耗优化方法

Optimization Method of Static Logic Circuit Power Consumption Based on Recursive Learning

由于影响静态逻辑电路功耗的因素较多,导致功耗的收敛性较低,因此提出基于递归学习的静态逻辑电路功耗优化方法。分别从静态功耗和动态功耗两个角度构建静态逻辑电路功耗模型,并引入了电源电压和电流参量,综合分析在不同电压环境下静态逻辑电路单元延时的标准差和均值。根据获取的延时数据,计算各个单元对应的功耗值。将电路的延时作为递归学习的敏感度函数,采用递归学习的方式实施对静态逻辑电路功耗收敛效果的优化。测试结果表明,设计方法可以实现FPRM逻辑电路功耗和混合极性XNOR/OR电路功耗的快速收敛。

Due to many factors affecting the power consumption of static logic circuits,the convergence of power consumption is low.Therefore,a power consumption optimization method for static logic circuits based on recursive learning is proposed.The power consumption model of static logic circuit is constructed from the perspectives of static power consumption and dynamic power consumption respectively,and the parameters of power supply voltage and current are introduced to comprehensively analyze the standard deviation and mean value of the delay of static logic circuit unit under different voltage environments.According to the acquired delay data,the power consumption value corresponding to each unit is calculated.Taking the delay of the circuit as the sensitivity function of recursive learning,the method of recursive learning is used to optimize the power consumption convergence effect of static logic circuits.The test results show that the design method can achieve fast convergence of the power consumption of FPRM logic circuits and mixed-polarity XNOR/OR circuits.