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CRNN心音分类系统硬件加速及实现

Hardware acceleration and implementation of CRNN heart sound classification system
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摘要 为提高心音分类算法的实时性并将该分类算法移植至资源有限的移动设备中,提出一种适用于CRNN心音分类系统的硬件加速器。根据卷积层和LSTM层运算特点,通过交错缓存和分片缓存减小内存耗用,采用滑动窗运算机制和HLS指令优化最大限度地增加运算并行度,在FPGA平台中实现该加速方案。实验结果表明,与通用CPU相较,该CRNN加速器实现了29.79倍加速效果,能效比为通用GPU的20.2倍,具有较好的使用价值。 To improve the real-time performance of the heart sound classification algorithm and transplant the classification algorithm to mobile devices with limited resources,a hardware accelerator suitable for CRNN heart sound classification system was proposed.According to the operational characteristics of the convolutional layer and the LSTM layer,the memory consumption was reduced through interleaved cache and sliced cache,while the sliding window operation mechanism and HLS instruction optimization were used to maximize the parallelism of operations,and this acceleration schema was realized on FPGA platform.Experimental results show that compared with the general CPU,the CRNN accelerator achieves 29.79 times of acceleration effect,and the energy efficiency ratio is 20.2 times of the general GPU,which has good use value.
作者 周李敏 孙静 杨宏波 潘家华 王威廉 ZHOU Li-min;SUN Jing;YANG Hong-bo;PAN Jia-hua;WANG Wei-lian(School of Information Science and Engineering,Yunnan University,Kunming 650500,China;Structural Heart Disease Ward,Fuwai Yunnan Cardiovascular Hospital,Kunming 650102,China)
出处 《计算机工程与设计》 北大核心 2022年第11期3071-3078,共8页 Computer Engineering and Design
基金 国家自然科学基金项目(81960067) 云南省重大科技专项基金项目(2018ZF017)。
关键词 心音分类 现场可编辑逻辑门阵列 递归卷积神经网络 并行计算 硬件加速 heart sound classification FPGA CRNN parallel computing hardware acceleration
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