NMS译码算法中优化比例因子的FPGA LDPC译码器

An FPGA-based LDPC decoder with optimized scale factor of NMS decoding algorithm

针对低密度校验码(Llow-density parity-check,LDPC)归一化最小和NMS(Normalized minimum sum)译码算法中由于尺度因子的不确定性导致译码算法硬件实现困难的问题,以空间数据系统协商委员会(CCSDS)标准中(8177,7154)近地空间LDPC码为研究对象,提出了一种尺度因子可变的NMS译码算法,它利用现场可编程门阵列(FPGA)的移位特性对校验节点的量化数据进行优化,最终实现了LDPC译码器功能。仿真和实验结果表明,所设计的基于FPGA的LDPC译码器采用NMS译码算法中的变尺度因子提高了解码性能、简化了硬件结构,加快了收敛速度,提高了纠错能力。

Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.