一种改进型可配置逻辑块的结构设计

Structural Design of an Improved Configurable Logic Block

可配置逻辑块(CLB)是FPGA中最重要的模块,其主要由查找表、选择器、触发器等子模块组成,可以通过配置来实现组合逻辑和时序逻辑,其性能直接影响到整个FPGA的表现。为了提高CLB的利用率和性能,提出了一种改进型的CLB结构。基于VPR平台对修改后的CLB结构进行架构建模,选用不同类型的基准电路测试了CLB结构对延时和面积等性能的影响。实验结果表明,改进后的结构在关键路径延时平均增大8.86%的前提下,所用CLB数量节省了24.88%,总面积减小了12.95%。且该结构能够在VPR中被正确描述与解析,测试结果对FPGA的结构设计与分析具有参考价值。

Configurable logic block(CLB) is the most significant module in FPGA, which mainly consists of look-up tables, multiplexers, flip-flops and other sub-modules that can be configured to implement combinational logic and timing logic, and its performance directly affects the performance of the whole FPGA.To improve the utilization and performance of CLB, an improved CLB structure is proposed. The modified CLB structure is architecture modeled based on the VPR platform, different types of reference circuits are selected to test the impact of the CLB structure on delay and area performance. The test result shows that the improved structure with 8.86% increase in critical path delay, the number of CLBs saves 24.88% and the area is reduced by 12.95%. And the structure can be correctly described and parsed in VPR, the test results have reference value for the structure design and analysis of FPGA.