基于埋层结构的高压功率MOS器件终端设计

Design of High Voltage Power MOS Device Terminal Based on Buried Layer Structure

为改善传统结终端延伸(JTE)结构的终端注入剂量偏低、终端对表面固定电荷敏感、终端尺寸优化不够等缺陷,设计了一种基于场板(FP)与埋层(BL)的新型终端结构,用于降低表面固定电荷对击穿电压的影响,并且通过提高JTE区域的掺杂剂量,同时优化表面电场,实现了终端电场更加均衡,提高了击穿电压及减少结终端尺寸。利用仿真软件对提出的新型终端结构进行仿真,对新结构的电场分布、击穿电流电压曲线、击穿电压随终端JTE区注入剂量变化和击穿电压随表面固定电荷Qf变化四个方面进行分析,结果表明:相比传统JTE终端,本文设计的新型终端尺寸缩短16%,耐压提升约20%,同时可靠性也有所提升。

In order to improve the defects of traditional junction terminal extension(JTE)structure,such as low terminal injection dose,sensitive terminal to surface fixed charge,insufficient terminal size optimization,a new terminal structure based on field plate(FP)and buried layer was designed to reduce the influence of surface fixed charge on breakdown voltage.By increasing the doping dose in JTE area and optimizing the surface electric field,the terminal electric field is more balanced,the breakdown voltage is increased and the terminal size is reduced.The proposed new terminal structure is simulated by using the simulation software.The electric field distribution,breakdown current and voltage curve,the change of breakdown voltage with the injection dose in the terminal JTE area and the change of breakdown voltage with the surface fixed charge Qf of the new structure are analyzed.The results show that compared with the traditional JTE terminal,the size of the new terminal designed in this paper is shortened by 16%,and the withstand voltage is increased by about 20%.At the same time,the reliability has also been improved.