基于RISC-V和密码协处理器的SOC设计

SOC design based on RISC-V and cryptographic coprocessor

为了保障工业互联网设备在计算资源有限的硬件上敏感数据的机密性,同时更好地满足其低延迟的需求,通过扩展指令,在开源蜂鸟E203 MCU(Micro Control Unit,微控制单元)的基础上扩展了适用于AES(Advance Encryption Standard,高级加密标准)、RSA复合加密场景的协处理器,组成拥有安全场景扩展的RISC-V SOC(System on Chip,片上系统)。与无扩展指令相比,协处理器加持下的AES 128 bit和RSA 1024 bit运算速度至少提升了230倍,在华虹40 nm工艺下,AES核综合后面积为30805μm^(2),物理设计后的硬核面积为44944μm^(2),吞吐率可达3.9 Gbps,RSA核综合后面积为94552μm^(2),物理设计后面积为129600μm^(2),吞吐率可达49.87 kbps。

To ensure the confidentiality of sensitive data on industrial internet hardware with limited computing resources,and to better meet its low-latency requirements,on the basis of the open-source Hummingbird E203 MCU,a coprocessor suitable for AES and RSA composite encryption scenarios is expanded to design a RISC-V SOC with extended security scenarios by extension instructions.The operating speeds of AES 128 bit and RSA 1024 bit under the co-processor support have in-creased by more than 230 times compared with implementation without extension instructions.Under the Huahong40nm process,the area of the AES core after synthesis is 30805 square micron,and after the physical design the hardcore area is 44944 square micron,the throughput rate can reach 3.9 Gbps;the area of the RSA core after synthesis is 94552 square micron,after physical design is 129600 square micron,the throughput rate can reach 49.87 kbps.