应用于时钟发生器的低噪声电荷泵设计

A Low Noise Charge Pump Design for Clock Generators

基于SMIC 0.13um CMOS工艺,设计了一款应用于能够输出任意频率的时钟发生器的电荷泵电路。该时钟发生器具有内部偏置电路,能够为电荷泵电路提供稳定的电源电压和镜像电流偏置,该电荷泵电路中采用了轨至轨传统跟随器电路结构,能够有效地抑制电荷泵电荷分享效应;并且通过加入互补开关管来减小了时钟馈通和电荷注入效应,后仿真结果表明,在电源电压为1.5V,电荷泵电流为2.5mA,调谐范围为0.15~1.1V时,充放电的最大静态电流失配小于0.3%;在输入频率为312.5MHz,输出时钟频率为625MHz时,100M环路带宽下,后仿真得到电荷泵输出端点相位噪声小于-201.8dBA@20kHz,等效到4/5/6分频器输出端点相位噪声为-116.8dBc@20kHz。流片测试结果的带内相位噪声与计算值基本一致。

Based on SMIC 0.13um CMOS process,a charge pump circuit is designed for a clock generator that can output any frequency.The clock generator has an internal bias circuit,which can provide stable power supply voltage and mirror current bias for the charge pump circuit.The charge pump circuit adopts a rail-to-rail traditional follower circuit structure,which can effectively suppress the charge pump charge sharing.The effect of clock feedthrough and charge injection is reduced by adding complementary switch tubes.The post-simulation results show that when the power supply voltage is 1.5V,the charge pump current is 4mA,and the tuning range is 0.15-1.1V,the charging and discharging The maximum quiescent current mismatch is less than 0.3%;when the input frequency is 312.5MHz,the output clock frequency is 625MHz,and the loop bandwidth is 100M,the post-simulation results show that the phase noise of the output terminal of the charge pump is less than-201.8dBA@20kHz,which is equivalent to the phase of the output 4/5/6 divider terminal Noise is-116.8dBc@20kHz.The in-band phase noise of the tape-out test results is basically consistent with the calculated value.