基于JESD204B协议的接收端电路设计

Receiver Circuit Design Based on JESD204B Protocol

设计了一款可应用于4通道、16 bit、2.5 GSa/s数模转换器的接口电路。单个通道采用4路并行传输的方法以降低电路的设计难度,并通过链路建立、数据处理、错误统计和模块解帧实现协议的数据链路层和传输层。搭建通用验证方法学平台与设计的接收端电路进行数据交互,提高验证效率。基于某65 nm工艺库对电路进行逻辑综合与版图设计,流片后的样片测试结果表明,接收端电路满足JESD204B协议的要求,单通道数据传输速率最高可达12.5 Gbit/s。

An interface circuit for 4-channel,16 bit,2.5 GSa/s digital to analog converter is designed.The single channel uses a 4-channel parallel transmission method to reduce the design difficulty of the circuit and implement the data link layer and transport layer of the protocol through link establishment,data processing,error statistics and module deframer.A universal verification methodology platform is built to interact with the designed receiver circuit to improve the verification efficiency.Based on a 65 nm process library,the logic synthesis and layout design of the circuit are carried out.The test results after the chip is taped out show that the function of the receiver circuit meets the requirements of JESD204B protocol,and the single channel data transmission rate can reach up to 12.5 Gbit/s.