基于AIG的多级逻辑电路延迟近似优化

AIG based delay optimization of multilevel logic circuits using approximate computing technique

在对多级逻辑电路延迟进行优化中,提出了一种针对关键路径中节点输出的近似替换方法,用于实现延迟优化.提出的算法先建立待优化电路的关键路径集合,然后通过选取每一条关键路径中错误率影响最小的节点构成待优化节点集,再结合提出的节点输出近似替换技术,在错误率约束下实现节点删除和关键路径压缩,进而达到多级逻辑电路延迟优化.提出的算法用C++和ABC工具内置命令编程实现,使用ISCAS85以及LGSynth91电路进行测试.实验结果显示,与已提出的常量替换方法相比,面积和延迟优化效果分别提升22.96%和31.49%.同时相较于最新提出的针对延迟优化的算法,在延迟优化效果相近的情况下,算法运行时间上有61.88%的提升.

In order to optimize the delay of multi-level circuits,an algorithm using the approximate replacement of the output node in critical path is proposed for delay optimization purposes.In the algorithm,those critical paths which can be optimized are searched first.Then,the nodes in each critical path with the lowest error rate are selected to form an approximate replacement node set.Finally,by deleting those nodes using approximate replacement under the constraint of error rate,the critical paths are shortened,and the delay is improved.The proposed algorithm is programmed with C++,built-in commands in ABC tools and tested with ISCAS85 and LGSynth91 benchmarks.The experimental results show that compared with the proposed constant replacement methods,the area and delay are improved by 22.96% and 31.49% respectively.Meanwhile,compared with the newly proposed algorithm,our algorithm running timing is improved by 61.88% while the optimization of delay and area remains similar.