类脑处理器异步片上网络架构

Asynchronous Network-on-Chip Architecture for Neuromorphic Processor

类脑处理器较深度学习处理器具有能效优势.类脑处理器的片上互连一般采用具有可扩展性高、吞吐量高和通用性高等特点的片上网络.为了解决采用同步片上网络面临的全局时钟树时序难以收敛的问题以及采用异步片上网络面临的链路延迟匹配、缺乏电子设计自动化工具实现和验证的问题,提出了一种异步片上网络架构——NosralC,用于构建全局异步局部同步(global asynchronous local synchronous,GALS)的多核类脑处理器.NosralC采用异步链路和同步路由器实现.实验表明,NosralC较同步基线,在4个类脑应用数据集下展现出37.5%~38.9%的功耗降低、5.5%~8.0%的平均延迟降低和36.7%~47.6%的能效提升,同时增加不多于6%的额外资源以及带来较小的性能开销(吞吐量降低0.8%~2.4%).NosralC在现场可编程门阵列(FPGA)上得到了验证,证明了该架构的可实现性.

Neuromorphic processors show extremely high energy efficiency advantages over traditional deep learning processors.The network-on-chip with high scalability,high throughput,and high versatility features is generally adopted as the on-chip communication and connection implementation of neuromorphic processors.In order to solve the problems of making the synchronous network-on-chip that adopts the global clock tree to achieve timing closure,matching link delay in the asynchronous network-on-chip,and lacking electronic design automation tools in implementation and verification of asynchronous network-on-chip,we propose a low-power asynchronous network-onchip architecture,NosralC,to build a global-asynchronous-local-synchronous multi-core neuromorphic processor.NosralC is implemented with asynchronous links and synchronous routers.The small amount of asynchronous design makes NosralC similar to the synchronous design and friendly to implementation and validation of asynchronous design using existing electronic design automation tools.Experiments show that compared with a synchronous counterpart baseline with the same function,NosralC achieves 37.5%-38.9%reduction in power consumption,5.5%-8.0%reduction in average latency,and 36.9%-47.6%improvement in energy efficiency in executing the FSDD,DVS128 Gesture,NTI-DIGITS,and NMNIST neuromorphic application datasets while increasing less than6%additional resource overhead and a small amount of performance overhead(0.8%-2.4%throughput decrease).NosralC is verified on the field programmable gate array(FPGA)platform and its implementability is proved.