面向RISC-V处理器的高速浮点单元设计

Design of High-Speed Floating-Point Unit for RISC-V Processor

浮点单元是高性能处理器的速度瓶颈之一,基于广泛应用的开源RISC-V浮点单元原型,设计了一种面向RISC-V处理器的高速浮点单元。对该原型中时序最差的浮点融合乘加、整数转浮点、除法开方子模块分别进行静态时序分析,并定位其中需要优化的关键模块。针对该浮点单元原型中存在的问题,提出基于算法优化和流水线优化的设计思路,设计基4 Booth-Wallace乘法模块替代原有多位宽乘法模块,设计基于二叉树的并行前导零检测模块替代原有串行前导零检测模块,增加了部分子模块的流水线级数。基于SMIC 55 nm工艺对优化设计前后的RISC-V浮点单元原型进行了性能评估,优化后的工作频率达到820 MHz,提升了39.46%,而面积开销增加了15.14%。

Floating-point unit is one of the speed bottlenecks of high-performance processor.Based on the widely used open-source RISC-V floating-point unit prototype,a high-speed floating-point unit for RISC-V processor is designed.Static timing analyses are performed for the submodules which have worst timing in prototype,including the floating-point fused multiply-add,integer-to-floating-point,floating-point divider and sqrt submodules.Next,the critical modules most in need of optimization are located.Then,the design methods are proposed based on algorithm optimization and pipeline optimization.A radix-4 Booth-Wallace multiplication module is designed to replace the original multi-bit wide multiplication algorithm.A parallel leading zero detection algorithm based on binary tree is designed to replace the original serial leading zero detection algorithm,and the pipeline stages of some submodules are increased.Based on the SMIC 55 nm technology,the performance of RISC-V floating-point unit prototype before and after the optimization are evaluated.The operating frequency reaches 820 MHz after optimization,increased by 39.46%,and the area is increased by 15.14%.