基于FPGA和B61580S3的1553B总线RT/MT功能的设计与验证

Design and verification of 1553B bus RT/MT function based on FPGA and B61580S3

1553B总线协议因具有优越的实时性、高度的数据可靠性以及可同时挂载多个终端等优势,在国内航空航天领域的电子交互网络中得到广泛使用。文中基于B61580S3协议芯片内置的16位缓冲模式实现了MIL-STD-1553B总线功能。采用VHDL硬件描述语言为FPGA设计了总线接口控制电路,通过FPGA对协议芯片的控制以及协议芯片内部数据自动解析和强大的中断机制,实现了RT/MT功能;通过测试台上位机软件对设计的1553B总线接口的测试与验证,结果表明接口设计可靠,传输误码率低,有较高的应用价值。

Because of its superior real-time performance,good data reliability and the ability to carry multiple terminals at the same time,the 1553B bus protocol is widely used in electronic interactive networks in the domestic aerospace field.This paper realizes the MIL-STD-1553B bus function based on the built-in 16 bit buffer mode of the B61580S3 protocol chip.The bus interface control circuit is designed for FPGA by using VHDL hardware description language,and the RT/MT function is realized through the FPGA’s control of the protocol chip,the automatic analysis of the internal data of the protocol chip and the powerful interrupt mechanism.The test and verification of the 1553B bus interface show that the interface design is reliable,the transmission bit error rate is low,and it has high application value.