在FPGA上实现对RS译码器的优化设计

Optimization Design of RS Decoder Based on FPGA

针对里德所罗门码(Reed Solomon,RS)译码在硬件实现时存在数据量大、消耗资源多等问题,基于CCSDS标准中的RS(255,223)码,根据欧几里得核心译码算法,在FPGA上实现对RS译码器的优化设计。本文提出采用乘法器因子矩阵方法将有限域中的乘法计算转换为加法运算,用异或操作在硬件中实现,简化硬件运算数据量;在欧几里得算法核心模块实现中,采用多项式除法电路和多项式乘法电路进行硬件电路设计,降低运算复杂度,可以有效节约硬件资源。通过FPGA测试验证,优化设计的译码器可以有效译码并具有较好的译码性能,完成最多16个码元数据的纠错。

Aiming at the problems of large data volume and resource consumption in the hardware implementation of Reed Solomon(RS)decoding,the RS decoder is optimized in FPGA implementation based on the RS(255,223)code in CCSDS standard and Euclid core decoding algorithm.In this design,the multiplier factor matrix method is proposed to convert the multiplication calculation in the finite field to the addition operation,and the exclusive OR operation is implemented in hardware to simplify the amount of hardware operation data.In the implementation of Euclid's core algorithm module,polynomial division circuit and polynomial multiplication circuit are used to design the hardware circuit,which can reduce the computational complexity and effectively save hardware resources.The FPGA test results show that the optimized decoder can effectively decode and has good decoding performance,and can correct up to 16 code data.