一种14位2MS/s逐次逼近型模数转换器的设计

Design of A 14-bit 2-MS/s Successive Approximation Register Analog-to-digital Converter

本文提出了一种14位2MS/s逐次逼近型模数转换器(Successive Approximation Register Analog-to-Digital Converter,SAR ADC)。电路在基于顶板采样和Vcm-Based电容切换时序的二进制权重电容电荷再分配型传统模数转换器的基础上,通过采用开关电容无源积分器和多输入对全动态比较器累加转换余差电压实现二阶噪声整形结构抑制信号带内噪声,使得本设计在同等采样电容阵列下融合了SAR ADC和ΔΣADC的优点,具有更高分辨率以及更低功耗。本设计采用SMIC0.18um CMOS工艺,仿真结果表明,在3.3V电源电压,2MS/s采样率下,功耗为1.95mW,过采样率(Over Sample Ration,OSR)为16时,信号噪声失真比(SNDR)为81.76dB,无杂散动态范围(SFDR)为89.14dB,有效位数(ENOB)为13.29位。

In this paper,a 14-bit 2-MS/s successive approximation analog-to-digital converter is proposed(Successive Approximation Register Analog-to-Digital Converter,SAR ADC).Based on the traditional analog-to-digital converter of binary weight capacitor charge redistribution type based on top-plate sampling and Vcm-Based capacitor switching timing,the second-order noise shaping structure is realized by using switched capacitor passive integrator and multi input to full dynamic comparator to accumulate the conversion residual voltage to suppress the signal in band noise.This design integrates SAR and ADC under the same sampling capacitor arrayΔΣADC has the advan-tages of higher resolution and lower power consumption.This design uses SMIC 0.18μm CMOS process,with supply voltage of 3.3V,sampling rate of 2 MS/s and the over sample rate(OSR)of 16.The simulation results show that the ADC consumes 1.95mWand achieves an SNDR of 81.76dB,SFDR of 89.14dB,resolution of 13.29bit.