提高码流输出∑-ΔADC转换率的方法

Improvement of Conversion Rate for ∑-Δ Modulator

码流输出的∑-ΔADC芯片与Sinc3滤波器,是伺服系统中电机相电流采样的常用器件与滤波器,而使用高精度输出时转换率较低的缺点,约束了其在同时要求高速与高精度场景中的应用。根据∑-ΔADC输出信号特点与Sinc3的工作原理,提出了两种提高滤波器转换率的方法,并基于Intel Cyclone IV FPGA实现设计。最后通过Modelsim仿真,芯片资源消耗与实验对方法进行比较与验证。仿真与实验结果表明,两种方法在工作时钟与抽取率不变的情况下能大幅提高转换率。

∑-Δ modulator with data stream output and sinc3 filter are widely used in servo system as current sampling component. However, because of the relative low conversion rate while keeping the high precision output, ∑-Δ modulator in high speed applications is greatly limited. According to the output signal of ∑-Δ modulator and the structure of sinc3,two new methods to improve the conversion rate were proposed and realized in this paper, and the feasibility and the advantage of the new methods were examined and compared by simulation, resource consumption and servo system experiment. As shown in the results, the conversion rate can be improved by the new methods while the clock and the decimation rate remains the same.