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适用于GaN栅极驱动的自适应死区时间控制电路

An Adaptive Dead Time Control Circuit for GaN Gate Drive
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摘要 设计了一种适用于GaN栅极驱动的自适应死区时间控制电路,该电路具有低延时、低功耗、高速、高开关频率的特点。电路通过单脉冲产生电路检测开关节点电压,以实现零静态功耗;加入互锁电路以防误触发,消除了由开关节点毛刺导致的上下管直通的现象。电路基于SMIC 0.18μm BCD工艺设计,仿真结果表明,死区时间可随负载变化而自适应调整,且当最坏情况开关节点电压的dv/dt=48 V/ns时,电路高低侧死区时间误差仅为1.59 ns和2.69 ns。 An adaptive dead time control circuit for GaN gate driver is proposed, with low time delay, low power, high speed, and high switching frequency. The switching node voltage was detected by a single-pulse generation circuit to achieve zero static power dissipation. An interlocking circuit was designed to avoid false triggering which may lead to a shoot-through state. The proposed circuit was designed in SMIC 0.18 μm BCD process. The simulation results show that the dead time is adaptively adjusted along with the load. When the dv/dt of switching node voltage is 48 V/ns, which is the worst working condition, the dead time error of the high and low side are only 1.59 ns and 2.69 ns respectively.
作者 程汉 叶益迭 潘春彪 奚争辉 CHENG Han;YE Yidie;PAN Chunbiao;XI Zhenghui(Faculty of Electrical Engineering and Computer Science,Ningbo University,Ningbo,Zhejiang315211,P.R.China)
出处 《微电子学》 CAS 北大核心 2022年第5期764-771,共8页 Microelectronics
基金 浙江省自然科学基金资助项目(LY20F010003) 宁波市自然科学基金资助项目(2019A610113) 国家自然科学基金资助重点项目(62131010) 宁波大学王宽诚幸福基金。
关键词 GAN 自适应死区时间控制 低功耗 互锁电路 GaN adaptive dead time control low power interlock circuit
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