14nm FinFET工艺下栅隔离型二极管的ESD防护性能研究

Study on ESD Protection Performance of Gated Diode in 14 nm FinFET Process

当集成电路工艺进步到鳍式场效应晶体管(FinFET)技术节点时,二极管仍广泛用于输入/输出端口(I/O)的静电放电(ESD)防护工程,但二极管单位宽度鲁棒性比平面工艺有所降低。文章基于14 nm FinFET工艺,对栅隔离型二极管的失效电流(I_(t2))、失效电压(V_(t2))、单位宽度失效电流(I_(t2)/Width)以及单位面积失效电流(I_(t2)/Area)进行了详细研究,并给出了ESD器件特性随尺寸参数的变化趋势。实测数据表明,I_(t2)/Width随着Fin数目(n_(fin))、沿Fin方向的倍乘因子(F_(n))、垂直于Fin方向的倍乘因子(Y_(array))等的增加均会有所降低,但I_(t2)/Area却有所提高,且开启电阻几乎不受n_(fin)和F_(n)的影响。

Diode is still widely used in I/O ESD application when the process advances to FinFET technology, though the robustness per unit width of the diode is lower than planar process. This paper detailed ESD performance parameters based on 14 nm FinFET process, such as failure current(I_(t2)), failure voltage(V_(t2)), failure current per unit width(I_(t2)/Width) and failure current per unit area(I_(t2)/Area) of Gated diode. The tendencies of ESD device characteristics with dimension parameters were given. It is found that the I_(t2)/Width decreases while the I_(t2)/Area increases with the increase of number of fins(n_(fin)), the multiplication factor along the fin(F_(n)) and the multiplication factor across the fin(Y_(array)). The on-resistance is almost not affected by n_(fin)and F_(n).