RapidIO交换芯片的静态时序约束设计

Design of static timing constraint for RapidIO switch chip

静态时序分析是目前通用的芯片时序验证的重要方法,其依赖于时序模型和时序约束。时序约束是检验设计电路时序的准则,好的时序约束可以正确地体现芯片的设计需求。针对RapidIO交换芯片中存在的多时钟域构成、高速通道的高速时钟频率要求,2x/4x绑定模式下多lane时钟同步等的特殊要求,以及较多的跨异步时钟处理存在的问题,文中提出一种多分组的全芯片时序约束,通过设置时钟定义、时钟组定义、端口延迟定义、时序例外和虚假路径等,以及修正和优化必要的setup time/hold time违例,解决RapidIO交换芯片静态时序分析中的时序违例等时序问题,实现时序收敛的目的。实验验证及流片测试结果表明,所有时序路径均满足时序要求,RapidIO芯片的时序约束设计正确、完备。

Static timing analysis is an important method of chip timing verification,which depends on timing model and timing constraints. Timing constraint is the criteria for checking the timing of design circuits. Good timing constraint can correctly reflect the design requirements of chips. In allusion to the multi-clock domain composition in RapidIO switching chip,high-speed clock frequency requirements for high-speed channels,special requirements for multi-lane clock synchronization in2x/4x bonding mode,and many problems in cross-asynchronous clock processing,a multi-group full-chip timing constraint is proposed. By setting clock definition,clock group definition,port delay definition,timing exception and false path,and correcting and optimizing the necessary setup time/hold time violation,timing problems such as timing violations in the static timing analysis of RapidIO switching chips are solved to achieve timing convergence. The experimental verification and chip testing results show that all the timing paths can meet the timing requirements,and the design of the timing constraint of RapidIO chip is correct and completed.