摘要
100 GB以上超高速以太网采用FEC(Forward Error Correction)技术来降低误码率,提升传输可靠性。针对目前以太网中RS(528,514)码和RS(544,514)码两种编解码规范并存,导致的FEC解码器结构冗杂、资源耗费严重、面积占用大等问题,文中将多模RS解码器的概念引入以太网FEC解码器设计,提出一种适用于100 GB及以上超高速以太网的双模RS解码器。通过对不同的编解码规范进行研究与分析,设计通用的SC、KES、CSEE模块并实现部分内存共享,采用并行设计与流水线处理来降低传输时延、提高吞吐量。在100 GB以太网中进行仿真实验,测试该双模解码器的功能完整性、资源开销以及功耗。结果表明,所设计的双模RS解码器能成功实现对两种FEC规范的解码,解码时延分别为93 ns,96 ns,相比于传统RS解码器,资源开销与功耗分别降低32.32%,17.34%。
FEC(forward error correction)technology is adopted for ultra-high-speed Ethernet over 100 GB to reduce bit error rate and improve the transmission reliability. In allusion to the coexistence of of RS(528,514) code and RS(544,514) code in Ethernet, which may cause complicated FEC decoder structure, serious resource consumption and large area occupation,the concept of multimode RS decoder is introduced into the design of Ethernet FEC decoder,and a dual-mode RS decoder suitable for ultra-high-speed Ethernet of ≥100 GB is proposed. The different encoding and decoding standards are researched and analyzed,general SC,KES,CSEE modules are designed and their partial memory sharing is realized,and parallel design and pipeline processing are used to reduce transmission delay and improve throughput. The functional integrity,resource overhead and power consumption of the dual-mode decoder are tested in the simulation experiments in 100 GB Ethernet. The results show that the designed dual-mode RS decoder can successfully acheive decoding of the two FEC standards. Its decoding delay is 93 ns and 96 ns respectively. In comparison with the traditional RS decoder,its resource cost and power consumption are reduced by 32.32% and 17.34% respectively.
作者
李继豪
沈剑良
陈艇
LI Jihao;SHEN Jianliang;CHEN Ting(Information Technology Institute,PLA Strategic Support Force Information Engineering University,Zhengzhou 450002,China)
出处
《现代电子技术》
2023年第4期35-40,共6页
Modern Electronics Technique
基金
国家科技重大专项核高基项目(2016ZX01012101)。
关键词
RS解码器
超高速以太网
双模解码器
内存共享
模块设计
仿真验证
性能分析
RS decoder
ultra-high-speed Ethernet
dual-mode decoder
memory sharing
module design
simulation verification
performance analysis