针对多线程应用程序的片上网络优化设计

On-chip network optimized design for multithreaded applications

在多线程程序执行过程中,遇到同步屏障(Barrier)时,进度快的线程需要等待进度慢的线程,导致执行进度快的处理器处于等待状态,不仅影响性能且浪费功耗。对基于片上网络的多核处理器来说,数据包在网络中的路由过程所耗费的时间占据了较多的线程执行时间。为了均衡多线程的执行进度提升性能,本文提出了线程感知的虚拟通道分配和片上网络路由方案:一种动态的为执行进度慢的线程优先分配虚拟通道的机制AVCA和关键线程拥塞避免的路由策略CTCAR。实验结果表明,与传统没有线程感知路由算法相比,本文所提出的组合方案可以有效降低多线程应用程序数据包在片上网络传输时的平均延迟。

During the execution of a multithreaded application, when encountering a barrier, the thread with fast progress needs to wait for the thread with slow progress, therefore causes the processor with fast execution progress to be in a waiting state, which not only affects the performance, but also wastes power consumption. For multi-core processors based on the on-chip network, the routing process of packets in the network occupies more thread execution time. In order to balance the progress of multiple threads and improve the performance, this paper proposes a thread-aware virtual channel allocation and on-chip network routing scheme: a dynamic mechanism AVCA for assigning virtual channels to threads with slow execution progress in priority, and routing for key thread congestion avoidance strategy CTCAR. The experimental results show that, compared with the traditional thread-unaware routing algorithm, the combined scheme proposed in this paper can effectively reduce the average delay of multi-threaded application packets in the on-chip network transmission.