用于物联网的可重构的祖冲之密码算法的硬件设计

Hardware Design of the Reconfigurable ZUC Cryptographic Algorithm for the Internet of Things

针对应用在资源有限的物联网中的祖冲之(ZUC)256密码算法,本文介绍了一种资源优化的ZUC-256密码算法的硬件实现方案,设计了面向资源优化的循环型ZUC-256密码算法的硬件架构和基于块随机存取存储器(BRAM)的可重构S盒(S-box)单元,从而有效地降低了资源消耗。硬件方案在现场可编程逻辑门阵列(FPGA)上进行了硬件验证,结果表明本文资源优化的循环架构中的各个硬件开销相比已有的方案有明显的降低。

Aiming at algorithm of ZUC-256 cryptography applied in resource-limited Internet of Things,this paper introduces a hardware implementation scheme of resource optimization algorithm of ZUC-256 cryptography.It designs a hardware architecture of circular ZUC-256 cryptographic algorithm for resource optimization and a reconfigurable S-box based on Block Random Access Memory(BRAM),which effectively reduce resource consumption.The hardware solution is synthesized on a Field Programmable Gate Array(FPGA)platform.The results show that the hardware overhead of the resource optimized loop architecture is significantly reduced compared with the existing schemes.