基于FPGA的Sobel边缘检测架构

Sobel edge detection architecture based on FPGA

本文提出了一种基于Field Programmable Gate Array(FPGA)实现的高效8-bitSobel边缘检测硬件架构,通过结构优化和引入流水线技术,不仅减少了硬件资源利用率,并且提高了系统运行的最大频率。与三种现有的Sobel边缘检测架构相比,第一种是传统的Sobel边缘检测结构,另外两种也是8-bitSobel边缘检测结构。结果表明,本文提出的8-bitSobel边缘检测结构比传统的Sobel边缘检测结构在硬件资源上减少了37.55%,运行速度上提高了14.74%.尽管与运行速度最快的8-bitSobel边缘检测结构相比在速度上降低了1.24%,但是在资源率上提高了25%。因此,本文提出的8-bitSobel边缘检测架构更适用于硬件资源有限的平台。

An efficient 8-bit architecture for Sobel edge detection on Field Programmable Gate Array(FPGA)board was proposed in the paper.By optimizing the hardware structure and adopting pipeline,the utilization rate of hardware resources is greatly reduced and the operating frequency was increased.A compare study was also been done based on the three previous methods.The first method is the traditional Sobel edge detection architecture,and the rest of the two are 8-bit Sobel edge detection architecture.Compare with the traditional Sobel edge detection architecture,the architecture we proposed in this papereduces the hardware resources by 37.55%and improves the running speed by 14.74%.Despite a 1.24%reduction compared to the fastest 8-bit Sobel edge detection architecture,but resource utilization rate was significantly improved by 25%.The results show that the architecture has the highest resource utilization rate in increase system operating frequency,which means our architecture proposed is more suitable for hardware platforms with limited hardware resources.