基于FPGA与TDC-GPX2的数字延时发生器设计

Design of digital delay generator based on FPGA and TDC-GPX2

传统的用于LIBS检测系统的延时发生器虽然具有较高的延时精度,但是存在体积较大、价格较高的缺陷,设计出一种基于FPGA与TDC-GPX2结合的、成本较低、能够满足LIBS使用的数字延时发生器是十分必要的。该延时器以FPGA为核心处理器,结合了等离子体光电检测电路模块、脉宽检测模块、按键输入模块、高速比较电路,FPGA内部通过计数器延时原理将信号进行延时,用外置键盘设置其延时量,时间测量模块测量延时前后两路信号时间差进行验证。实验测得的数据和结果表明,该数字延时发生器输出信号的上升沿小于4 ns,下降沿小于3 ns,延时精度较高,工作性能稳定,可以满足实际应用需求。

Although the traditional delay generator for LIBS detection system has high delay accuracy,it has the defects of large size and high price.It is necessary to have a digital delay generator that can meet the requirements of LIBS.The delayer uses FPGA as the core processor,and combines the plasma photoelectric detection circuit module,pulse width detection module,key input module,and high-speed comparison circuit.The FPGA delays the signal through the counter delay principle,and uses an external keyboard to delay the signal.Set the delay amount,and the time measurement module measures the time difference between the two signals before and after the delay for verification.The experimental data and results show that the rising edge of the digital delay generator output signal is less than 4ns,the falling edge is less than 3ns,the delay accuracy is high,and the working performance is stable,which can meet the needs of practical applications.