摘要
循环冗余校验(CRC)码是诸多信道编码方式中最常用的一种编码,也是一种检错概率高且容易硬件实现的检错码,因检错能力强、容易实现而得到广泛应用。首先,本文介绍了循环冗余校验的算法原理,分析了CRC校验码的具体运算过程;其次,本文在原算法的基础上提出一种高速并行CRC算法,并以CRC-CCITT为例,推导出8位并行运算的CRC-CCITT逻辑关系式;最后,本文根据推导的8位并行运算的逻辑关系式,描述了8位并行的CRC-CCITT硬件实现电路。将该算法与现有的查找表法的性能进行分析比较发现,该算法具有节省逻辑资源、运行速度快等特点。
Cyclic redundancy check(CRC)code is one of the most commonly used code in channel codes.It is an error detection code with high detection probability and easy hardware implementation.It is widely used for its simple implementation and strong error detection ability.Firstly,this paper introduces the algorithm principle of cyclic redundancy check,and analyzes the specific calculation process of CRC.Secondly,this paper proposes a high-speed parallel CRC algorithm,and takes CRC-CCITT as an example to derive the CRC-CCITT logic relation of 8-bit parallel computing.Finally,according to the deduced logic relation of 8-bit parallel computing,the hardware implementation circuit of 8-bit parallel CRC-CCITT is given.Compared with the existing lookup table methods,the algorithm has the characteristics of saving logical resources and high speed.
作者
仇晓涛
Qiu Xiaotao(CEC Defense Technology Company Limited,Nanjing 210000,China)
出处
《无线互联科技》
2023年第2期115-117,168,共4页
Wireless Internet Technology
关键词
循环冗余校验
生成多项式
并行计算
FPGA
cyclic redundancy check
generator polynomial
parallel computing
FPGA
