一种晶上互连网络中负载均衡容错路由算法

A Load-Balancing Fault-Tolerant Routing Algorithm in Network on Wafer

晶上系统融合预制件组装和晶圆级异构集成等先进理念,借助晶圆级互连的高带宽、低延迟、低功耗等显著优势,使信息系统的设计指标获得连乘性增益。但由于晶圆基板中本身制造良率和拼接过程中的不确定性,系统中的预制件互连可能存在节点故障或链路故障,同时会产生网络负载不均衡等问题。因此,提出一种自适应的负载均衡容错路由算法,算法依据中介中心性对2D-Mesh拓扑进行核心区域的划分,并利用限定条件限制数据包进入核心区,同时基于容错感知结构实现故障避免。实验仿真表明,在复杂故障及热点流量模型场景下,相较于现有的片上网络容错路由算法,所提算法在饱和注入率上平均提高了11.55个百分点,饱和吞吐率平均提高了22.7个百分点。

The system-on-wafer integrates advanced concepts such as dielets assembly and wafer-level heterogeneous integration, and leverages the significant advantages of wafer-level interconnection such as high bandwidth, low latency, and low power consumption to achieve multiplicative gains in the design indicators of information systems. However, due to the uncertainty of the manufacturing yield in the wafer substrate and the splicing process, the dielets interconnection in the system may experience node failure or link failure, and meanwhile, problems such as network load imbalance may occur. Therefore, this paper proposes an adaptive load-balancing fault-tolerant routing algorithm. The algorithm divides the core area of the 2D-Mesh topology according to the betweenness centrality, and restricts the data packets from entering the core area with limited conditions, and realizes fault avoidance based on the fault-tolerant perception structure. The experimental simulation shows that in the complex fault and hot-spot traffic model scenarios, compared with the existing on-chip network fault-tolerant routing algorithms, our algorithm increases the saturated injection rate by 11.55 percent on average, and the saturated throughput rate by 22.7 percent on average.