高速采样信号数字下变频研究

Research of Digital Down Converter Based on High-Speed Sampling Signal

对于高速采样信号接收处理,基本结构数字下变频无法满足需求。提出了一种灵活并行度的低复杂度数字下变频结构,给出了16并行度的数字下变频实例,分析了资源消耗情况。通过仿真表明,该并行结构的数字下变频功能正确,同时资源消耗较低,能较好地满足高速采样信号的大吞吐需求。

The digital down converter with normal structure is not able to meet processing of high-speed sampling signal. A low-complexity structure for digital down converter with flexible degree of parallelism is proposed. Meanwhile, an example is provided which degree of parallelism is 16 and the consumption of hardware resource is analyzed. Simulation results show that the function of proposed digital down converter is correct and consumption of hardware resource is acceptable. Hence, the proposed structure for digital down converter is satisfied with processing of high-speed sampling signal.