面向三维忆阻阵列的状态逻辑计算

Stateful logic computation in three-dimensional memristor crossbar array

基于忆阻存储阵列的状态逻辑电路是打破“冯·诺依曼瓶颈”,实现存内计算的有效途径。然而,目前针对存内状态逻辑电路的研究多以二维忆阻存储阵列为基础平台,缺少对更复杂的三维忆阻存储阵列中状态逻辑实现的讨论。相比于平面二维阵列,三维忆阻存储阵列拥有更大的存储密度和更丰富的器件连接关系,能对状态逻辑门的构建提供更灵活的配型方法。因此,有必要对状态逻辑门在三维存储阵列中的配型和级联过程进行专门讨论。立足平面堆叠型三维忆阻存储阵列,从基本状态逻辑门的实现以及支持级联的综合映射方法2个方面对复杂状态逻辑计算过程实现进行研究。首先,分析并总结了平面堆叠型三维忆阻存储阵列中器件的连接关系,并据此得出实现两输入布尔逻辑的状态逻辑门配型要求。其次,提出一种复合状态逻辑门,通过将逻辑输入与逻辑输出共享同一个忆阻器,来一步实现复杂逻辑功能(例如,定义为ONOR),节省复杂状态逻辑计算过程的步骤与器件数目。最后,还给出了基于三维忆阻存储阵列中复杂状态逻辑计算实现的自动化综合映射方法。对LGsynth91基准的测试结果表明,与当前二维阵列中的最优映射结果相比,提出的基于三维忆阻存储阵列的综合映射方法实现了层间的逻辑计算,并且节省了41.1%的阵列使用面积。在引入ONOR复合门之后,完成计算需要的逻辑操作步骤、忆阻器数目、阵列使用面积分别进一步降低了8.6%,18.8%和50.5%。

The stateful logic based on memristor is an effective way to break the"von Neumann bottleneck"and realize the Processing In Memory(PIM).However,the current research on stateful logic circuits in memory is mostly based on two-dimensional memristor memory array,and there is a lack of discussion on the implementation of stateful logic in more complex three-dimensional memristor memory array.Compared with the planar two-dimensional array,three-dimensional memristor array has greater storage density and richer device connectivity,which may provide a more flexible matching method for the constructing the stateful logic gates.Therefore,it is necessary to discuss the cascading and achieving process of stateful logic gates in three-dimensional memristor array.In this work,based on the planar stacked 3D memristor array,we study the implementation of complex stateful logic computing process from two aspects:the implementation of basic stateful logic gates and the integrated mapping method supporting cascade.Firstly,the connection relationship of devices in planar stacked 3D memristor arrays is analyzed and summarized.Based on this,the matching requirement of stateful logic gate for two-input Boolean logic is obtained.Secondly,a compound state logic gate is proposed.Logic inputs and logic output shares the same memristor,which can realize a complex logic function in one step(for example,defined as ONOR).It saves the number of steps and devices in complex stateful logic calculation process.Finally,an automatic synthesis mapping method based on complex stateful logic calculation in 3D memristor arrays is presented.Test results on the LGsynth91 benchmark show that,compared with the optimal mapping results in the current two-dimensional array,the proposed comprehensive mapping method based on the three-dimensional memristor array achieves the logic calculation between layers,and saves 41.1%of the used area of the array.After the introduction of the ONOR compound gate,the logical operation steps,the number of memristors and the used area of the array are further reduced by 8.6%,18.8%and 50.5%,respectively.