SoC芯片UVM平台自动化开发系统

Automatic System of Developing UVM Testbench for SoC

数据通信So C芯片规模大、接口数量繁多且配置复杂,开发过程需要完备的设计验证环境。市场上部分EDA工具已集成自动化验证平台,但它们一般只能搭建基本框架,无法自动支持非标准总线协议,需要较多手动更改,导致开发模块、子系统和系统级UVM验证平台及测试用例耗时较长。本文介绍了一种可自动提取验证平台关键信息、高效并智能化生成大规模So C芯片UVM验证平台的系统,根据用户配置自动分析RTL设计代码,抓取端口信号,并自动生成验证环境平台代码。本系统已经成功应用于多个数百亿晶体管规模的数通So C芯片验证工作,UVM平台开发时间缩短为之前的五分之一,大大提高了芯片研发效率,增强了平台代码质量和测试配置的灵活性、以及平台的可维护性。本系统可推广至更多SoC产品开发。

Data communication SoC are with great scale,numerous I/O interfaces and complicated configurations,which require complete verification platforms.Most of the existing EDA tools in the market can build verification testbenches with basic framework but need quite some manual work to change and add more customized components and bus protocols,which takes long time to build UVM testbenches for module,subsystem and SoC levels and to develop test cases correspondingly.In this article we introduce an automatic system which we developed to build UVM testbenches especially for complicated data communication SoC more efficiently and intelligently.It can automatically analyze RTL codes and signals according to user configuration,and generate verification platform codes.The system has been proven in SoC products with tens of billion transistors inside,where the UVM testbenches development time are dramatically reduced down to one fifth of that before.It greatly promotes SoC development efficiency,improve code quality,configuration flexibility and maintainability.It can be deployed to more SoC products development as well.