离子注入静电干扰对刻蚀速率的影响浅析

Influence of Ion Implantation Electrostatic Interference on Etching Rate

伴随半导体器件特征尺寸的逐渐缩小,在芯片制作过程中对各种污染缺陷的控制越发重要。离子注入可以达到设计掺杂纯度和注入精度的要求,但与此同时离子注入也具有负面效应,会影响到器件的电性参数和器件的良率。文章主要阐述因离子注入机晶片架内静电干扰导致刻蚀速率发生变化,进而引起缺陷形成的过程。通过改进离子注入机产生静电干扰的位置,达到消除缺陷的目的,为半导体设备传输过程中的升级改进提供有益参考。

Along with the gradual reduction of the characteristic size of semiconductor devices, the control of various defects in the chip fabrication process has become more and more important. Ion implantation can achieve the design doping purity and implant precision, but at the same time, ion implantation also has negative effects, which can affect the electrical parameters and the yield of the device. The paper mainly describes the process of scanning defect formation in flash memory chip production due to the change of etching rate caused by electrostatic interference in the chip holder of ion implant. By improving the position of electrostatic interference generated by ion implantation machine, the defects in the process of ion implantation can be eliminated, which provides a useful reference for the upgrade and improvement of semiconductor equipment in the process of transport.