基于FPGA的高性能硬件EtherCAT主站研究

Research of EtherCAT Master Station with High Performance Hardware Based on FPGA

随着技术的不断进步,高端应用场合对EtherCAT主站的性能提出了越来越高的要求。传统的软件EtherCAT主站使用Windows或Linux操作系统实现,主站的性能和稳定性完全依赖操作系统的实时性,且主站的抖动一般为微秒级别,不能满足高端应用的需求;同时,传统的时钟同步算法以第一从站的时钟作为系统时钟,具有一定的局限性。对此,文章首先对目前EtherCAT主站研究的现状进行阐述;然后提出了一种基于FPGA的硬件EtherCAT主站方案以及一种基于FPGA主站时钟的DC同步算法,并对硬件EtherCAT主站实现的方法进行了描述;最后采用6台通用伺服驱动器作为从站设备,对主站系统进行了实验验证。实验结果表明,所设计的主站通信数据帧抖动仅为5 ns,且搭配本文所述的时钟同步算法,各从站间同步信号SYNC0中断实时同步,能满足各高端应用场景的需求;同时由于FPGA代码的可移植性,该主站可灵活应用于不同的硬件平台,具有很强的工程指导意义。

With the continual technical advancement, the requirements for the performance of the EtherCAT master station are raised in high-end applications. The EtherCAT master station configured with traditional software runs Windows or Linux operating system, completely depending on the real-time capability of the operating system regarding performance and stability, and suffering from jitter generally at the microsecond level, so it can hardly meet the requirements in high-end applications. In addition, the clock of the first slave station is used as the system clock for the traditional clock synchronization algorithm, imposing certain limitations.Therefore, this paper first elaborates the current status of the EtherCAT master station research, and then proposes an FPGA-based hardware EtherCAT master station scheme and a DC synchronization algorithm based on the FPGA master clock, followed by the description on the implementation method of the hardware EtherCAT master station;the final part contains the experimental verification on the proposed master station system with six general-purpose servo drives as the slave devices. Base on the verification results, with only 5 ns data frame jitter in the master station communication of the current design and with the clock synchronization algorithm described herein, SYNC0 interrupts are synchronized in real time among slaves, which can meet the requirements of various high-end application scenario;moreover this master station can be flexibly applied to different hardware platforms due to the portability of FPGA codes, which has a strong engineering guiding significance.