卷积神经网络的硬件加速设计

Design of Hardware Acceleration System Based on FPGA

为解决目标检测算法随识别率的提高而当前普通的处理器无法满足算法的计算需求和内存需求等问题,该文采用一种基于FPGA的设计方法对卷积神经网络进行硬件加速,使用HLS技术设计YOLOv2目标检测算法,对算法中的各个网络层次进行相应的优化,并在FPGA加速器中对图像权重数据、像素数据进行复用以降低访问次数和数据量从而降低系统时延。实验结果表明,系统性能达28.37 GOPs(giga operations per second,10亿次运算/s),功耗为2.60 W,与CPU(E5-2620v4)相比,系统性能是CPU的7.14倍,功耗仅占CPU的2.8%,与当前目标检测系统相比具有一定优势。

In order to solve the problem that the target detection algorithm increases with the recognition rate and the current ordinary processor cannot meet the computational demand and memory requirement of the algorithm. An FPGA-based design method is used to accelerate the convolutional neural network in hardware. The YOLOv2 target detection algorithm is designed using HLS technology,and each network level of the algorithm is optimized accordingly.The experimental results show that the system performance reaches 28.37 GOPs(giga operations per second) and the power consumption is 2.60 W. Compared with the CPU(E5-2620v4),the system performance is 7.14 times of the CPU and the power consumption is only 2.8% of the CPU,which has certain advantages compared with current target detection systems.