基于FPGA的SDN中QoS保障算法的设计与实现

Design and implementation of QoS guarantee algorithm in SDN based on FPGA

传统网络越发难以面对复杂化的网络结构,于是诞生了一种新型网络架构,即软件定义网络(SDN)。SDN数据中心的业务流主要有长流和短流,长流有持续时间长、时延不敏感、带宽需求高的特点;而短流持续时间短、时延敏感程度高、带宽需求低。短流的流量占总流量不足20%,但流量条数则约占总流量数的80%以上;长流的流量占总流量80%以上,但流量条数不足总流量数的20%。研究发现,在出端口队列中长流往往在短流前,造成短流长时间等待,极易引发网络拥塞。根据2种业务流特点提出排队机制和路由优化保障机制,将短流设置为高优先级队列,由SDN控制器优先调度排队机制;将长流设置为低优先级队列,同时采用路由保障算法进行补偿。路由保障算法首先删除不满足长流带宽需求的链路,再计算最短时延路径。为了提升本设计的算法效率,使用FPGA和万兆以太网对SDN中业务流进行仿真,并在FPGA上仿真验证了本设计对于网络的时延、带宽的优化与FPGA并行运算的优势。

The traditional network is increasingly difficult to face the complex network structure,so a new network architecture is born,namely software defined network(SDN).The service flow of SDN data center mainly includes long stream and short stream.The long stream has the characteristics of long duration,insensitive delay and high bandwidth demand;while short flow has short duration,high delay sensitivity and low bandwidth requirement.Short flows account for less than 20%of the total traffic,but the number of traffic bars is about 80%or more of the total traffic;long flows account for more than 80%of the total traffic,but the number of traffic bars is less than 20%of the total traffic.It is found that the long flow is often ahead of the short flow in the outgoing port queue,causing the short flow to wait for a long time,which is very likely to cause network congestion.The design proposes a queuing mechanism and a route optimization guarantee mechanism based on the characteristics of the two service flows,setting the short flows as high-priority queues,which are prioritized and scheduled by the SDN controller;setting the long flows as low-priority queues,while using a route guarantee algorithm for compensation.The routing assurance algorithm first removes the links that do not meet the bandwidth requirements of the long flows,and then calculates the shortest delay path.In order to improve the efficiency of the algorithm of this design'FPGA and 10G ethernet are used to simulate the service flow in SDN,and simulate on FPGA to verify the advantages of this design for the optimization of network delay,bandwidth and FPGA parallel computing.