一种中值滤波快速系统的FPGA实现

Implementation of a Median Filtering Acceleration System Using FPGA

针对传统焊缝图像滤波实时性差、处理速度慢的问题,提出了一种中值滤波快速系统的FPGA实现方案。首先,在Quartus II软件开发平台中进行系统总体设计,完成了上位机交互模块、地址发生器模块、数据流控制模块和流水卷积中值滤波算法模块的模块化设计,并在数据流控制模块的时序作用下,实现像素分块读取功能及数据的流水线处理功能,进而构建快速滤波卷积核,执行流水中值滤波算法;其次,在Modelsim仿真平台下验证该系统的功能;最后,在MATLAB环境下将本文设计方案与传统的2种中值滤波方案处理的结果进行对比。实验结果表明:以分辨率为600×400的焊缝图像为例,本方案能在保证峰值信噪比的情况下,极大提高处理速度和数据吞吐量,满足图像实时处理的要求。

Aiming at the poor real-time performance and slow processing speed of traditional weld image filtering methods,a scheme of fast median filtering system based on FPGA development platform is proposed.Firstly,the overall design of the system is carried out in Quartus II software development platform,and the modular design of host computer interaction module,address generator module,data stream control module and pipelining convolution median filter algorithm module is completed.Under the timing action of data stream control module,the reading function of pixel block and the pipelining processing function of data are realized,and the fast filter convolution core is constructed to execute pipelining median filter algorithm.Secondly,the function of the system is verified under the Modelsim simulation platform.Finally,the weld image filtering processing results of this design scheme are compared with those of two traditional median filtering schemes in MATLAB software development platform.The filtering processing result of the weld image whose resolution is 600×400 shows that this scheme can greatly improve the processing speed and data through-put under the condition of ensuring the peak signal-to-noise ratio,and meet the requirements of real-time processing of image.