一种高速时钟信号数字调相器设计

A digital phase modulation technology for high-speed clock signals

时钟调相电路在高速串行数据传输(Serializer-Deserializer,Serdes)和时钟数据恢复等技术中得到广泛应用,如何实现结构简单、精度高的多相时钟,是提高Serdes性能的核心.本文提出了一种改进的粗精调结合的数模转换结构,提高了时钟信号的多相位插值的精度.该时钟电路是一种由数字信号控制的64相位的高速时钟信号调相电路,采用多组双尾电流源的双路差分恒流放大器和单尾电流源的双路差分恒流放大器,分别实现粗调和微调,完成基于电流的相位调节.本文提出的数字信号控制高速时钟信号调相电路,具有频率高、稳定性强、精度高、结构简单、易于实现等优点.基于以上方法,完成了基于SMIC 55 nm CMOS标准工艺的3.5 GHz、64相位输出的高速时钟调相电路,模块版图面积为0.039 mm2,具有较小的面积;电路理论分析表明,采用这种结构的相位插值器,DNL和INL出现的最大偏移度数都在1°左右,具有较高的精度.

Clock phase modulation circuits are widely used in high data-rate Serializer-Deserializer(Serdes)technology and clock data recovery circuits.To implement the low-complexity and high accuracy multi-phase clock,is a key part for improving Serdes’s performances.In this paper,an improved digital-to-analog conversion structure combining coarse and fine adjustment is proposed,which improves the accuracy of multi-phase interpolation of the clocks.It is a 64-phase high-speed clock signal phase modulation circuit.In this circuit,the dual differential constant current amplifiers with multiple independent current sources and the dual differential constant current amplifiers with shared current sources are used to realize the combination of coarse adjustment and fine adjustment.This digital phase modulated clock has the advantages of low complexity,high frequency,strong stability and high precision.The high-speed clock phase modulation circuit was implemented based on SMIC 55 nm CMOS technology,the layout area is 0.039 mm2.The theoretical analysis of the circuit shows that,with the phase interpolator structure,the maximum deviation of DNL and INL is about 1°.