基于FPGA的改进单比特接收机门限设计方法研究

An Improved Threshold Algorithm Based on FPGA for Monobit Receivers

与传统数字接收机相比,单比特数字接收机具有大带宽和快速运行的优势。这些优势归功于低比特模拟-数字(A/D)转换和简化的傅里叶变换的使用,它减少了相关的操作过程,降低了计算负担,使单比特数字接收器能够快速响应。然而,这种用法缩小了单比特数字接收器的双信号动态范围,限制了其在双信号检测中的应用。为了解决这个问题,在单比特接收机中引入了单元平均恒虚警(CA-CFAR)算法,并结合现有的补偿矩阵算法提出了一种新的自适应阈值处理方法,以提高单比特数字接收机在双信号检测中的性能。仿真结果表明,所提出的方法可以有效拓宽双信号动态范围,提高双信号检测的成功率。此外,还进行了FPGA仿真以证明该算法的可实现性,为单比特接收机的工程设计提供了一定的参考。

Compared with conventional digital receivers,monobit digital receivers have the advantages of large bandwidth and fast operating speed.These advantages should be credited to the use of low-bit analog-to-digital(A/D)conversion and simplified Fourier transform,which reduces relevant operation processes and lowers computation burden,enabling monobit digital receivers to respond quickly.Nonetheless,the dual-signal dynamic range of monobit digital receivers is narrowed,limiting their application in dual-signal detection.To address this problem,a new adaptive threshold algorithm is proposed,which employs the compensation matrix algorithm and introduces the cell-averaging constant false alarm rate(CA-CFAR)algorithm to improve the performance of monobit digital receivers in dual-signal detection.The simulation results show that the proposed algorithm can effectively widen the dual-signal dynamic range and increase the success rate of dual-signal detection.In addition,FPGA simulation is also carried out to prove the feasibility of the proposed algorithm.The findings of this study are expected to provide some reference for the engineering design of monobit digital receivers.