SiC MOSFET重复雪崩能力提升的芯片结构优化方法

Chip Structure Optimization Method for Improving Repetitive Avalanche Capability of SiC MOSFET

SiC MOSFET的高速开关工况易诱发巨大的d i/d t,从而在电路的感性负载上引发过电压,导致器件进入雪崩状态。在多次雪崩冲击后,器件易发生重复雪崩失效。针对SiC MOSFET芯片元胞结构中栅氧化层薄弱导致器件耐重复雪崩冲击能力较差的问题,进行芯片元胞结构优化研究,以增强芯片耐重复雪崩能力,提升器件可靠性。首先,研究SiC MOSFET器件重复雪崩失效机理,开展SiC MOSFET器件重复雪崩失效测试,基于失效测试结果建立SiC MOSFET重复雪崩失效可靠性评估模型;其次,针对SiC MOSFET芯片元胞结构提出了栅极底部蚀刻、P-well区扩展、JFET顶部削弱三种优化结构,并研究三种优化结构对SiC MOSFET芯片SiO 2/SiC界面处碰撞电离率和垂直电场强度的影响;最后,基于SiC MOSFET雪崩失效可靠性评估模型,对比分析了三种不同优化结构SiC MOSFET的可靠性。研究结果表明SiC MOSFET器件栅极蚀刻元胞结构具有更高的重复雪崩失效可靠性,相关研究成果为SiC MOSFET器件耐重复雪崩失效能力提升的芯片元胞设计奠定理论基础。

High speed switching condition of SiC MOSFET is easy to induce huge d i/d t,which causes over-voltage on the inductive load of the circuit,causing the device into repetitive avalanche condition.After multiple avalanche shocks,the device is prone to experience repetitive avalanche failure.Aiming at the problem that the weak gate oxide layer in the cell structure of SiC MOSFET chips leads to poor resistance to repeated avalanche impact,the optimization of chip cell structure is carried out to enhance the repeated avalanche resistance of the chip and improve the reliability of the device.Firstly,the repeated avalanche failure mechanism of SiC MOSFET devices was studied,and the repeated avalanche failure test of SiC MOSFET devices was carried out.Based on the failure test results,a SiC MOSFET repeated avalanche failure reliability evaluation model was established.Secondly,for the cell structure of SiC MOSFET chips,three optimized structures are proposed:gate bottom etching,P-well region expansion,and JFET top weakening.The effects of three optimized structures on the collision ionization rate and vertical electric field strength at the SiO 2/SiC interface of SiC MOSFET chips were studied.Finally,based on the SiC MOSFET avalanche failure reliability evaluation model,the reliability of SiC MOSFETs with three different optimized structures was compared and analyzed.The results show that the gate etched cell structure of SiC MOSFET devices has higher reliability of repeated avalanche failure.The relevant research results lay a theoretical foundation for the chip cell design of SiC MOSFET devices with improved repetitive avalanche failure resistance.